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Carry select adder is the key circuit to achieve high-speed arithmetic operations. This paper presents the Efficient Approximation Carry Select Adder (EA-CSLA) involved in eradicating the carry 1 input path in LSB and attains a reduced amount of delay and hardware simplicity. Furthermore, this EA-CSLA utilizes an algorithmic cell split-up technique which diminishes the propagation delay in all parts of the circuit. The EA carry select adder design includes approximate full adder blocks with less gate count and reduced power consumption. This design is synthesized in Encounter-Cadence 90 nm tool up to GDSII level using Verilog language. Hardware implementation is done and verified through Xilinx System generator and the device Spartan 6 XSLX4T CSG324 is used. The EA carry select adder attains less area, reduced delay, error percentage and delay-entire power product than exact and present adders. The proposed efficient approximation circuit attains a considerable decrease in entire power utilization than existing approximate adder circuits.

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