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In VLSI based system design; optimum design is preferred in terms of area, delay and power. In the era of miniaturization the speed is the most important parameter in VLSI design. To achieve greater speed the designer must concentrate on reduction in delay. Generally the total delay consists of logic delay and path delay. For achieving delay optimization either path delay or logic delay can be modified. By re-arranging the architecture such that to modify interconnects, the delay can be reduced in the design of the system and speed can be comparatively increased. In this work, the authors propose a novel methodology for the construction of FIR filter design as a delay optimized one. The delay reduction is achieved using the reduction in the path delay,. The retimed MAC unit cell is used as a sub-component in the construction of FIR filter to obtain the required reduction. This construction was implemented using Xilinx software tool with the FPGA Spartan-3E and Virtex device.

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